Ultra-low energy per cycle oscillator topology

ABSTRACT

In described examples of an integrated circuit (IC), an oscillator includes Schmitt trigger delay cells connected in a ring topology. The Schmitt trigger delay cells have a high input threshold approximately equal to Vdd and a low input threshold approximately equal to Vss to increase delay through each cell. An output buffer receives a phase signal from an output terminal of one of the Schmitt trigger delay cells and converts a transition phase signal to a faster transition clock signal. The output buffer has control circuitry that generates non-overlapping control signals in response to the phase signal, to control an output stage to generate the fast transition clock signal while preventing short circuit current in the output stage.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No. 15/958,980, filed Apr. 20, 2018, which claims priority to Indian Provisional Application No. 201741025967, filed Jul. 21, 2017, entitled “Ultra-Low Energy per Cycle Oscillator Topology,” each of which is incorporated by reference herein.

TECHNICAL FIELD

This relates to ultra-low energy per cycle oscillator topology.

BACKGROUND

As the “internet of things” (IoT) becomes more widespread, small portable or autonomous devices are being powered by micro-batteries or energy harvesting systems. In such devices, minimal power consumption is important. An oscillator operating at a low frequency may be used to implement a wake-up timer. In many cases, the low frequency oscillator does not need to have good accuracy.

SUMMARY

In described examples of an integrated circuit (IC), an oscillator includes Schmitt trigger delay cells connected in a ring topology. The Schmitt trigger delay cells are coupled to a first power bus and to a second power bus. The Schmitt trigger delay cells have: a first input switch threshold approximately equal to a voltage provided on the first power bus; and a second input switch threshold approximately equal to a voltage provided on the second power bus.

The oscillator may also include an output buffer having an input coupled to receive a phase signal from an output terminal of one of the Schmitt trigger delay cells. The output buffer has an output stage to provide a clock signal. Also, the output buffer includes pre-drivers to generate non-overlapping control signals to control the output stage in response to the phase signal, in a manner that produces little or no short circuit current in the output stage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an example sensor system that includes an ultra-low power oscillator.

FIG. 2 is a plot of current vs. time for the system of FIG. 1.

FIG. 3A and FIG. 3B together is a schematic of an example ultra-low power oscillator.

FIG. 4 is plot of bias current vs. temperature for the example oscillator of FIG. 3A, FIG. 3B.

FIG. 5 is plot of voltage vs. time for various phases within the example oscillator.

FIG. 6 is plot of voltage vs time illustrating the high threshold of the Schmitt trigger inverters within the example oscillator.

FIG. 7 is plot of voltage vs. time illustrating the low threshold of the Schmitt trigger inverters within the example oscillator.

FIG. 8 is plot of voltage vs. time for non-overlap control signals in the output buffer of FIG. 3B.

FIG. 9 is plot of oscillator period vs. supply voltage for output signal of the example oscillator.

FIG. 10 is plot of frequency vs. supply voltage for the example oscillator.

FIG. 11 is plot of oscillator current vs. supply voltage for the example oscillator.

FIG. 12 is plot of frequency vs. temperature for the example oscillator.

FIG. 13 is a flow diagram of operation of an example ultra-low power oscillator.

DETAILED DESCRIPTION

In the drawings, like elements are denoted by like reference numerals for consistency.

Advances in the ultra-low power sensor platforms and Internet-of-Things (IoT) have led to a development of many new applications, such as environmental monitoring systems (temperature/gas/humidity sensors, thermostats, intruder detection, etc.), health monitoring systems (blood glucose and eye pressure monitors, etc.), and other monitoring systems. These systems usually operate from limited energy sources, such as a coin cell or an energy harvested source. Heavily duty-cycled operation with extreme power gating techniques are often used in these systems to reduce the average power consumption and to extend their lifetime. For such applications, a low “standby” or “quiescent current” (Iq) is desirable to attain average power dissipation on the order of nanowatts (nWs).

An example system described herein may achieve an Iq that is only a few nano-amperes (nA). A sample and hold (S/H) technique running on a very low frequency clock may provide good sensor results. For example, an oscillator that generates a low frequency clock signal may be operated in the sub 10 KHz range.

For many applications, an oscillator generating a low frequency clock does not need to have good accuracy. However, because the oscillator must operate continuously, it contributes to Iq, and therefore very low current consumption is beneficial. An example oscillator circuit described herein may use a ring topology of delay elements. The example described herein may use Schmitt trigger delay elements in the ring topology. The Schmitt trigger delay elements are designed to have switching threshold for the input signal that are approximately equal to the high and low supply voltages, in order to increase delay time provided by each delay element and thereby reduce a number of delay elements required to produce a low frequency signal.

The phase signals generated by each of the Schmitt trigger delay elements may have a relatively slow rise and fall time. One of the phase signals may be buffered by a digital buffer to create a clock signal that has a faster rise and fall time for use by other digital logic within an application system. An example ultra-low power non-overlap buffer is described herein that generates non-overlapping control signals, in response to a phase signal with relatively slow transitions, to control an output stage to generate a clock signal that has relatively fast transitions in a manner that essentially blocks short circuit current from flowing in the output stage. The example ultra-low power non-overlap buffer circuit described herein consumes less than 500 pA of current and provides transition times of <10 ns. In this manner, Iq of the example oscillator circuit may be reduced to an extremely low level.

FIG. 1 is a block diagram of an example sensor system 100 that includes a wakeup timer 101 that relies on an ultra-low power oscillator. FIG. 2 is a plot illustrating current vs. time for the system of FIG. 1. In this example, wake-up timer 101 performs the duty cycling of sensors 102, analog front end (AFE) 103, micro controller unit (MCU) 104 and wireless transmission circuits 105. Data sensing circuits 102 and transmission circuits 105 may operate with different duty cycles and accuracies, depending on the end target application. Sensors 102, AFE 103, MCU 104 and wireless transmission system 105 may be implemented using known or later developed low power designs. Wakeup timer 101 may be implemented using an ultra-low power oscillator to generate a low frequency clock signal that is described in more detail hereinbelow, along with a counter or other type of state machine to count a certain number of clock cycles and logic to wake up the rest of the system periodically. Power to operate sensor system 100 may be provided by a battery or capacitor 107 and/or by energy harvested from the environment (such as solar, vibration, heat, electromagnetic fields, etc.) by a known or later developed energy harvesting element 106. Power management unit 108 may perform various tasks, such as charging battery/capacitor 107 using harvested energy, adjusting voltage levels provided to system components such as AFE 103 and MCU 104, etc., using known or later developed power management techniques.

Referring to FIG. 2, duty cycle (D) 210 illustrates an example duty cycle for the sensor system 100 of FIG. 1. During sleep mode, standby current consumed mainly by the wakeup timer is low. Each period of system activity causes a current spike, such as illustrated at 211. With the duty cycled active power on the order of low nanowatts, the total system power is dominated by the wakeup timer and standby power consumption. An MCU may have an integrated low power timer circuit to perform system timing during its standby state. However, in conventional MCUs, an integrated system timing may consume over 300 nA, which may produce a total current consumption curve as illustrated by plot 212. Ultra-low power timer 101 (FIG. 1), also referred to herein as “nano timer” 101, may consume less than a few nA to produce a total current consumption curve as illustrated by plot 213. A reduction in quiescent current required to operate nano timer 101 is indicated at 214.

FIG. 3A and FIG. 3B together is a schematic of an example ultra-low power oscillator 300 that may be used to implement nano timer 101 of FIG. 1. In a fast CMOS (complementary metal oxide semiconductor) process, challenges exist for generation of large time constants in a range of milliseconds (ms) to seconds (s) on-chip at sub-10 pico-Joule per clock cycle (pJ/cycle) of energy. To limit or avoid short circuit currents, and to reduce power overhead in bias generation circuits, techniques described herein may allow operation across a wide range of supply voltage and temperature, with ease of portability across process nodes. Example oscillator 300 is an ultra-low energy KHz oscillator circuit. In this description, examples include: circuit techniques to reduce the oscillator energy consumption and to realize larger time-periods using a ring oscillator core 301; and a non-overlap buffer circuit 302 that provides faster transition times at ultra-low currents.

A current starved ring oscillator topology is suitable for ultra low power operations. The example oscillator core 301 uses a three-stage ring oscillator core made of Schmitt trigger delay cells 311, 312 and 313, biased using ultra low magnitude currents provided by weak current sources 314-316. A complete schematic is shown for Schmitt trigger delay element 311. Schmitt trigger delay elements 312 and 313 have a similar circuit. Schmitt trigger delay element 311 receives supply current from a voltage supply buss (Vdd) via weak current source 314 that is a p-type MOS transistor. Weak current source 317 is an n-type MOS transistor that returns current to ground voltage buss (Vss). Similar weak current sources 315, 316, 318, 319 are coupled to supply a limited supply current to Schmitt trigger delay elements 312, 313. Each weak current source 314-319 is coupled to bias current generator 303 and is configured to operate as a current mirror to mirror the bias current produced by bias current generator 303. In this example, bias current generator 303 produces a bias current that is approximately 650 pA. This example has three Schmitt trigger delay elements, but another example may have more Schmitt trigger delay elements to create a periodic signal that has a longer period. Likewise, fewer delay elements may be used to create a periodic signal that has a shorter period.

Bias Generator

Bias current generator 303 provides an approximately 650 pA reference current (Ibias) to the oscillator current sources 314-319 and to current sources 345-348, which are used with buffer circuit 302. Bias current generator 303 determines the power consumption of the oscillator stages and adds to the power overhead. A very low value for Ibias (on the order of sub-nAs) is preferred to achieve an ultra-low power operation and to generate larger delay values.

This example uses a β-multiplier reference current generator circuit to generate a bias current (Ibias) of approximately 650 pA. Transistors 320-323 (M0-M3) operate in the subthreshold region, and Ibias generated can be calculated as shown in expression (1).

Ibias=(nVT/R)·ln(K)  (1)

where n is the subthreshold slope factor, VT is the thermal voltage, and K is a ratio of aspect ratios of the transistors M1/M0. For K=4/3, n is approximately equal to 1.721, VT=25.85 mV at 27 C, R=20 MΩ, and Ibias can be calculated to be 640 pA from the expression (1). Resistor 324 (R) may be implemented in a binary weighted form to trim for process (±90 pA) and mismatch (±300 pA, 3-sigma) variations in Ibias.

FIG. 4 shows simulated Ibias characteristics with mismatch across an operating temperature range of −40 C to 125 C and a supply voltage range of 1.0V to 3.3V. The bias current that flows through resistor 324 is proportional to absolute temperature (PTAT).

Oscillator

FIG. 3A shows a three-stage current starved oscillator core 301 and the detailed circuit of delay cell 311. This example has inverting Schmitt trigger delay cells, because of their immunity to noise and disturbances. However, in another example, non-inverting delay cells may be implemented. An N-stage oscillator core, biased with a reference current of Ibias (650 pA), consumes a total average current of approximately N*Ibias/2=(975 pA), due to the periodic operation of each delay cell.

Conventionally, one or more of the following options could be used for generating a very low frequency timing signal in a ring oscillator topology: (a) low magnitude bias currents; (b) larger number of delay stages at a cost of increased current consumption; and/or (c) a large load capacitance (CL) (pFs) at a cost of increased chip area. In the example oscillator 301, a larger delay per stage is generated by using an ultra-low magnitude Ibias of 650 pA, accompanied by the CMOS Schmitt trigger high and low threshold levels being set at approximately the supply and ground voltages, respectively.

FIG. 5 is plot of voltage vs. time for three phases PH1 531, PH2 532, and PH3 533 within the oscillator 301 of FIG. 3A. Delay element 311 (FIG. 3A) begins its charging and discharging phases to produce output signal PH2, but only after input signal PH1 reaches the VSS and VDD threshold voltage levels, respectively. Delay element 312 begins its charging and discharging phases to produce output signal PH2, but only after input signal PH2 reaches the VSS and VDD threshold voltage levels, respectively. Similarly, delay element 313 begins its charging and discharging phases to produce output signal PH1, but only after input signal PH3 reaches the VSS and VDD threshold voltage levels, respectively. For example, for Vdd=1.8V and Vss=0.0V, in response to PH3 phase signal 533 reaching approximately 1.8 volts at trigger point 534, delay element 313 is triggered, which causes PH1 phase signal 531 to start falling. Similarly, in response to PH1 phase signal 531 reaching approximately 0.0 volts at trigger point 535, delay element 311 is triggered, which causes PH2 phase signal 532 to start rising.

FIG. 6 is plot of voltage vs. time illustrating the high threshold of the Schmitt trigger delay cells within example oscillator 301 of FIG. 3A. In this example, the high threshold point for Schmitt trigger delay cells 311-313 is designed to be approximately equal to the VDD supply voltage. The high threshold operation of Schmitt trigger delay cells 311 is illustrated in FIG. 6; however, Schmitt trigger delay cells 312, 313 operate in a similar manner. A high to low transition in PH2 phase signal 532 is produced by the set of transistors Mn1 to Mn4 of FIG. 3A, in response to PH1 phase signal 531. For a portion of each cycle, such as in the vicinity of time line 641, while PH1 phase signal 531 is at ground potential, PH2 phase signal 532 is held at VDD, internal node 328 (Vxn) of FIG. 3A is at VSS as illustrated by Vxn signal 628, and internal node 327 (Vyn) of FIG. 3A is at (VDD−Vth,n) as shown by Vyn signal 627. In this example, VDD is 1.8V, the n-type gate-source threshold voltage (Vth,n) is approximately 0.6V, and therefore (VDD−Vth,n) is approximately 1.2V. As PH1 signal 531 rises slowly from a VSS level, Vxn node 328 (FIG. 3A) charges to (VDD—Vth,n) through the subthreshold conduction of Mn2, as shown in FIG. 3A and illustrated by Vxn signal 628 in the vicinity of time line 643. Bypass transistor Mn4 (FIG. 3A) provides the needed charging current during this period. In the time duration between time line 641 and time line 643, pull-down transistor Mn3 (FIG. 3A) is in its super cut-off state with a negative gate-source voltage (Vgs), and the PH2 signal 532 is held at VDD.

As PH1 signal 531 voltage rises above (VDD−Vth,n) level as shown at time line 642, pull-down transistor Mn3 (FIG. 3A) begins to enter into a subthreshold region of operation. However, nodes Vyn 327 and PH2 remain undisturbed at (VDD−Vth,n) and VDD, respectively, because the ultra-low bias current (650 pA) required by Mn1 is now provided by transistor Mn2 and bypass transistor Mn4 of FIG. 3A. In response to PH1 signal 531 reaching the VDD level (Vth,n above Vyn voltage) at time line 643, pull-down transistor Mn3 begins to conduct and initiates the discharge phase of PH2 signal 532.

The subthreshold operation of pull-down transistor Mn3 defines the high threshold point 534 of the Schmitt trigger delay cell in this example. Also, in this example, bypass transistor Mn4 (FIG. 3A) is designed to be stronger than transistor pull-down transistor Mn3, in order to keep pull-down transistor Mn3 turned off for a longer period of time. Bypass transistor Mn4 can be made stronger by making the channel width of transistor Mn4 wider than the channel width of pull-down transistor Mn3. To provide an input threshold near Vdd, the channel width of bypass transistor Mn4 should be at least 1.3 times the channel width of pull-down transistor Mn3. In this example, the channel width of bypass transistor Mn4 is approximately three times the channel width of pull-down transistor Mn3. In other examples, an even larger range of difference between bypass transistor Mn4 and pull-down transistor Mn3 may be designed to increase the threshold closer to Vdd.

FIG. 7 is plot of voltage vs. time illustrating the low threshold of the Schmitt trigger delay cells within the oscillator 301 of FIG. 3A. In this example, the low threshold point for Schmitt trigger delay cells 311-313 is designed to be approximately equal to the VSS supply voltage. The low threshold operation of Schmitt trigger delay cell 311 is illustrated in FIG. 7; however, Schmitt trigger delay cells 312, 313 operate in a similar manner. A low to high transition in PH2 phase signal 532 is produced by the set of transistors Mp1 to Mp4 (FIG. 3A) in response to PH1 phase signal 531, in a similar manner to the high to low transition described with reference to FIG. 6.

For a portion of each cycle, such as in the vicinity of time line 741, while PH1 phase signal 531 is at VDD potential, PH2 phase signal 532 is held at Vss, internal node 325 (Vxp) of FIG. 3A is at VDD as shown by Vxp signal 725, and internal node 326 (Vyp) of FIG. 3A is at (VSS+Vth,p) as shown by Vyp signal 726. In this example, VSS is 0.0V, the p-type gate-source threshold voltage (Vth,p) is approximately 0.6V, and therefore (VSS+Vth,p) is approximately 0.6V. As PH1 signal 531 falls slowly from the VDD level, Vxp node 325 (FIG. 3A) discharges to (VSS+Vth,p) through the subthreshold conduction of Mp2 (FIG. 3A), which is illustrated by Vxp signal 725 in the vicinity of time line 743. In the time duration between time line 741 and time line 743, pull-up transistor Mp3 (FIG. 3A) is in its super cut-off state with a positive gate-source voltage (Vgs), and the PH2 signal 532 is held at VSS.

As PH1 signal 531 falls below (VSS+Vth,p) level as shown at time line 742, pull-up transistor Mp3 (FIG. 3A) begins to enter into a subthreshold region of operation. However, nodes Vyp 326 and PH2 remain undisturbed at (VSS+Vth,p) and VSS, respectively, because the ultra-low bias current (650 pA) required by Mp1 is now provided by the transistor Mp2 and bypass transistor Mp4 (FIG. 3A). In response to PH1 signal 531 reaching the VSS level (Vth,p below Vyp voltage) at time line 743, Mp3 begins to conduct and initiates the charging phase of PH2 signal 532.

The subthreshold operation of pull-up transistor Mp3 defines the high threshold point 535 of the Schmitt trigger delay cell 311 in this example. Also, in this example, bypass transistor Mp4 (FIG. 3A) is designed to be stronger than transistor Mp3, in order to keep pull-up transistor Mp3 turned off for a longer period of time. Transistor Mp4 can be made stronger by making the channel width of transistor Mp4 wider than the channel width of transistor Mp3. To provide an input threshold near Vss, the channel width of bypass transistor Mp4 should be at least 1.3 times the channel width of pull-up transistor Mp3. In this example, the channel width of bypass transistor Mp4 is approximately three times the channel width of pull-up transistor Mp3. In other examples, an even larger range of difference between bypass transistor Mp4 and pull-up transistor Mp3 may be designed to increase the threshold closer to Vss.

The oscillation frequency of example oscillator 301 (FIG. 3A) with the CMOS Schmitt trigger delay cells 311-313 is given by expression (2).

Fosc=Ibias/(2*N*CL*VDD)  (2)

For Ibias=650 pA, load capacitance (CL) of FIG. 3A=60 fF, VDD=1.8 V, N=3, and frequency of oscillation (Fosc) can be calculated from expression (2) to be approximately 1 KHz. According to expression (2), frequency of the proposed oscillator design is sensitive to process and temperature variations only through the Ibias, and is inversely proportional to VDD. In this example, a PTAT current source is used for Ibias, and the supply voltage is allowed to vary from 1.0 V to 3.3 V. High performance applications may use the following at a cost of additional power overhead: a constant bias current source or an Ibias generator that tracks VDD variations, and coarse supply regulation techniques.

Non-Overlap Buffer Circuit

Referring again to FIG. 3A, the PH1, PH2 and PH3 phase signals in ultra-low current oscillator 301 have relatively slow rise and fall times, due to a very low magnitudes of charging and discharging currents. To avoid causing large short circuit currents within digital load circuits in the rest of the sensor system 100 (FIG. 1), the oscillator output signal 340 needs to be buffered strongly to provide faster transition times (on the order of <10 ns) before being provided to those digital load circuits. In this example, a non-overlap buffer configuration 302 provides buffering with no short circuit current flow.

Current starved pre-drivers 341-344 have skewed switching thresholds to generate non-overlapping signals Vn 350 and Vp 351 from phase signal PH1. Pre-driver 341 receives supply current from a voltage supply buss (Vdd) via weak current source 345 that is a p-type MOS transistor. Pre-driver 342 receives supply current from Vdd via weak current source 346 that is a p-type MOS transistor. Weak current source 347 is an n-type MOS transistor that returns current to ground voltage buss (Vss) from pre-driver 343. Weak current source 348 is an n-type MOS transistor that returns current to Vss from pre-driver 344. Each of the weak current sources 345-348 is coupled to bias current generator 303 and is configured to operate as a current mirror to mirror the bias current produced by bias current generator 303. In this example, bias current generator 303 produces a bias current that is approximately 650 pA. This example has two sets of pre-drivers, but another example may have more or fewer pre-drivers to create non-overlapping control signals.

The skewed switching thresholds for pre-drivers 341-344 are caused by the circuit topology with weak current sources 345-348. For example, the switching threshold of pre-driver 341 is reduced from Vdd by the voltage drop produced by weak current source 345. Conversely, the switching threshold of pre-driver 343 is raised from Vss by the voltage drop produced by weak current source 347.

PMOS transistor 352 and NMOS transistor 353 form the output stage of buffer circuit 302 and are driven by non-overlapping control signals 350, 351. Therefore, PMOS transistor 352 and NMOS transistor 353 turn ON at non-overlapping times and avoid short circuit current from VDD to VSS. This operation also provides relatively fast signal transitions to the final inverter stages 354 in this example.

FIG. 8 is plot of voltage vs. time for non-overlap control signals Vn 350 and Vp 351 (FIG. 3B) in the output buffer 302 (FIG. 3B). As phase signal PH1 531 rises from Vss, pre-driver 341 switches at low threshold 851 to cause control signal Vp 351 to switch from a low level to high level. Approximately 0.1 ms later, pre-driver 343 switches at high threshold level 850 to cause control signal Vn 350 to switch from a low level to a high level. As phase signal 531 falls from Vdd, pre-driver 343 switches at high threshold level 852 to cause control signal Vn 350 to switch from the high level to a low level. Approximately 0.1 ms later, pre-driver 341 switches at low threshold 853 to cause control signal Vp 351 to switch from the high level to a low level. In this manner, non-overlapping control signals cause pull-up transistor 352 and pull-down transistor 353 (FIG. 3B) to switch in a manner that prevents both of them against turning ON at the same time, so no short circuit current will flow through them.

In this example, non-overlap buffer circuit 302 (including the final inverter stages 354 of FIG. 3B) consumes a total average current of approximately 500 pA and provides an output signal transition time less than 10 ns with a load capacitance (CLoad) 355 of approximately 50 if.

Test Results

An example ultra-low power oscillator circuit as described herein was fabricated in a 130 nm CMOS process. The oscillator occupies an active area of 0.027 mm2 (177 μm×152 μm). At room temperature, the test oscillator example (including bias generation, oscillator core, and non-overlap buffer) consumes a total current of 2.8 nA from 1.8 V supply voltage to generate a 1 KHz clock signal (5 pJ/cycle). The bias current generator consumes a 1.3 nA (2*Ibias) current. The oscillator core consumes 975 pA (3*Ibias/2) of current. The non-overlap buffer circuit consumes a current of 525 pA. The test oscillator example circuit achieves an ultra-low energy performance of 1.16 pJ/cycle at a 1 V supply voltage, consuming 2.18 nA current to generate a 1.87 KHz frequency of oscillation. The example oscillator design operates across a wide supply voltage range of 1.0 V to 3.3 V, and a temperature range of −40° C. to 125° C.

FIG. 9 is plot of oscillator period vs. supply voltage for the output signal of the test oscillator example. FIG. 10 is plot of frequency vs. supply voltage for the test oscillator example. The measured frequency versus supply voltage characteristics agrees with expression (2) hereinabove. Effect of Ibias on the time period/frequency and current consumption of the oscillator circuit are measured under three different Ibias settings of 550 pA, 712 pA and 1305 pA. Frequency of oscillation is inversely proportional to VDD. The test oscillator example circuit has a measured supply voltage dependence of 0.0613%/mV over the supply voltage range of 1.0 V to 3.3 V, which is acceptable in the relaxed performance applications of many sensor systems. For stringent application requirements, a pseudo Vdd regulation may be added to the example design at a cost of additional power consumption.

FIG. 11 is plot of oscillator current vs. supply voltage for the test oscillator example. The oscillator current consumption increases with the supply voltage, due to a reduction in the non-overlap time window in the output buffer circuit.

FIG. 12 is a plot of the frequency versus temperature characteristics of the test oscillator example circuit measured from five chips. The measured frequency rises almost linearly with the temperature, due to a PTAT characteristic of the bias current in this example and shows a temperature sensitivity of 0.417%/° C. The oscillator consumes a total current of 2.45 nA, 3 nA and 7.8 nA at −40° C., 27° C. and 125° C., respectively, from a 1.8V supply.

FIG. 13 is a flow diagram of operation of an example ultra-low power oscillator as described in more detail herein. At 1302, phase signals (such as PH1, PH2 and PH3 of FIG. 3A) are circulated through a ring topology of Schmitt trigger delay cells, such as Schmitt trigger delay cells 311-313 (FIG. 3A).

At 1304, delay through each Schmitt trigger delay cell is increased by setting the switching threshold approximately equal to the supply voltage that is used to power the Schmitt trigger delay cells. This may be done by bypassing the pull up and pull-down transistors with bypass transistors to keep the pull-up and pull-down transistors turned off until the input signal reaches the Vdd or Vss supply voltage, as described in more detail in with regard to FIG. 6 and FIG. 7.

At 1306, non-overlapping control signals are produced within an output buffer by using pre-drivers that have skewed switching thresholds and are coupled to receive one of the phase signals. In this example, the weak current sources coupled to the Vdd and Vss supply bus provide an extra voltage drop that skews the thresholds of the respective pre-driver, as described in more detail with regard to FIG. 8.

At 1308, a pull-up and a pull-down transistor in an output stage of output buffer are controlled with the non-overlapping control signals in a manner that prevents the pull-up transistor and the pull-down transistor against being turned on at the same time. In this manner, a short circuit current is prevented from passing through the pull-up transistor and the pull-down transistor, as described in more detail with regard to FIG. 8.

At 1310, delay through the Schmitt trigger delay cells may be further increased by current starving the Schmitt trigger delay cells. This may be done using weak current sources that mirror an ultra-low bias current, as described in more detail with regard to weak current sources 314 and 317 (FIG. 3A).

System Example

Referring again to FIG. 1, oscillator 300 (FIG. 3A, 3B) may be coupled to sensors 102, AFE 103, MCU/DSP 104 and/or wireless interface logic 105 for use as a clock signal by the various circuit blocks. Sensors 102 may be any of a variety of known or later developed circuits or interfaces to sense external conditions, parameters, signals, etc. Processing logic 104 may be coupled to control operations of sensing logic 102. Also, system 100 may include additional interface logic and storage circuitry.

Wake-up timer 101, sensors 102, AFE 103, MCU/DSP 104, wireless interface 105 and power management logic 108 may all be fabricated on a semiconductor substrate and formed into an integrated circuit (IC) chip using known or later developed semiconductor fabrication techniques. Each IC chip may be mounted on a lead frame or direct mounted on another substrate and packaged in a protective enclosure using known or later developed IC packaging techniques.

Energy storage 107 provides energy to oscillator 300 and to the other circuitry within system 100. Energy storage 107 device may be a battery in some examples. In other examples, energy storage 107 may be a capacitor or inductor that is charged by energy scavenging from the surrounding environment, such as by near field coupling, light energy, thermal energy, vibration energy, etc. Low power operation of oscillator 300 conserves power available from energy storage 107. In some examples, the IC chip may include energy harvesting logic 106. In other examples, an energy harvesting device may be coupled to the packaged IC chip. In some examples, energy storage device 107 may be fabricated on the IC chip as a capacitor. In other examples, a battery 107 may be coupled to the packaged IC chip.

Thus, an ultra-low energy, KHz oscillator circuit suitable for heavily duty cycled applications is described herein. The example KHz oscillator employs an ultra-low current biasing scheme, larger delay generation techniques and non-overlap buffer circuits to reduce the oscillator total power consumption. A chip prototype of the proposed circuit was fabricated in a 130 nm CMOS process. The oscillator achieves an ultra-low energy performance of 1.16 pJ/cycle, consuming a 2.18 nA current from 1 V supply to generate 1.87 KHz frequency of oscillation. The performance of the ultra-low power example was verified across a wide supply voltage range of 1.0 V to 3.3 V, and a temperature range of −40° C. to 125° C.

Other Examples

In described examples, an oscillator circuit includes a non-overlapped buffer. In another example, a low power non-overlapped buffer as described may be used alone in another application to receive a signal having a relatively slow transition rate and convert it to a signal having a relatively fast transition rate with a low power consumption.

In described examples, a Schmitt trigger ring topology oscillator circuit is followed by a non-overlapping buffer to convert a phase signal having a relatively slow transition rate into a clock signal having a relatively fast transition rate. In another example, a Schmitt trigger ring topology oscillator circuit as described herein may be used without a non-overlapping buffer, such as where digital logic short circuit current is not an issue.

In another example, a Schmitt trigger ring topology oscillator circuit as described may be used with another type of buffer.

In described examples, the Schmitt trigger delay cells are connected to Vdd and Vss voltage supplies. Other examples may have different supply voltages, such as Vss and −Vdd. References herein to a “high threshold” and a “low threshold” are relative. For example, in a Vss/−Vdd system, the “high threshold” would refer to Vss, and the “low threshold” would refer to −Vdd.

To further reduce total current consumption, example embodiments perform current starving of the Schmitt trigger delay cells and non-overlap output buffer using weak current sources. In another example, current starving may be omitted on some or all of the cells.

In the example described herein, an ultra-low bias current of approximately 650 pA is generated to control the weak current sources. In another example, a higher or a lower bias current may be generated and used as described herein, with a corresponding change in total current consumption.

In the example described herein, the oscillator output signal is referred to as a “clock signal” that may be used to clock other digital logic. In another example, the oscillator output signal may be used as a frequency signal for another application besides clocking digital logic.

The examples described herein include a sensor system. In other examples, an ultra-low power oscillator as described herein may be used in other types of systems to provide a low frequency periodic signal for various applications, such as: a wake up function, a clock signal, a low frequency periodic signal, and other applications.

In example embodiments, the term “approximately” means that a value or range of values is either a stated value or range of values or within plus or minus 10% from that stated value or range of values.

In this description, the term “couple” and derivatives thereof mean an indirect, direct, optical, and/or wireless electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, through an indirect electrical connection via other devices and connections, through an optical electrical connection, and/or through a wireless electrical connection.

Modifications are possible in the described examples, and other examples are possible, within the scope of the claims. 

What is claimed is:
 1. A device comprising: an oscillator that includes: a first bias input configured to receive a first bias voltage; a second bias input configured to receive a second bias voltage; and a set of stages coupled in series that each include: an input node; an output node; a first bias transistor coupled between a voltage source node and a first node that includes a gate coupled to the first bias input; a second bias transistor coupled between a second node and a ground node that includes a gate coupled to the second bias input; a first transistor and a second transistor coupled in series between the first node and the output node such that a third node is defined therebetween; a third transistor coupled between the third node and the ground node that includes a gate coupled to the output node; a fourth transistor and a fifth transistor coupled in series between the output node and the second node such that a fourth node is defined therebetween; and a sixth transistor coupled between the fourth node and the voltage source node that includes a gate coupled to the output node.
 2. The device of claim 1 further comprising a buffer coupled to the oscillator that includes: a first buffer bias input coupled to the first bias input of the oscillator; a second buffer bias input coupled to the second bias input of the oscillator; a buffer input node coupled to the output node of a final stage of the set of stages of the oscillator; and a buffer output node.
 3. The device of claim 2, wherein the buffer further includes: a first buffer bias transistor coupled between the voltage source node and a fifth node; a second buffer bias transistor coupled between a sixth node and a ground node; a first driver that includes a seventh transistor and an eighth transistor coupled in series between the fifth node and the ground node; and a second driver that includes a ninth transistor and a tenth transistor coupled in series between the voltage source node and the sixth node.
 4. The device of claim 3, wherein the buffer further includes: a third driver coupled to the first driver; and a fourth driver coupled to the second driver.
 5. The device of claim 4, wherein the buffer further includes: an eleventh transistor that includes a source coupled to the voltage source node, a gate coupled to the third driver, and a drain coupled to the buffer output node; and a twelfth transistor that includes a source coupled to the ground node, a gate coupled to the fourth driver, and a drain coupled to the buffer output node.
 6. The device of claim 1 further comprising a bias circuit that includes: a first bias output coupled to the first bias input of the oscillator; a second bias output coupled to the second bias input of the oscillator; a resistor coupled between the voltage source node and a fifth node; a seventh transistor coupled between the fifth node and the second bias output that includes a gate coupled to the first bias output; and an eighth transistor coupled between the second bias output and the ground node that includes a gate coupled to the second bias output.
 7. The device of claim 6, wherein the bias circuit further includes: a ninth transistor coupled between the voltage source node and the first bias output that includes a gate coupled the first bias output; and a tenth transistor coupled between the first bias output and the ground node that includes a gate coupled the second bias output.
 8. The device of claim 6, wherein the bias circuit further includes a start-up circuit that includes: a capacitor coupled between the voltage source node and a seventh node; a ninth transistor coupled between the first bias output and the ground node that includes a gate coupled to the seventh node; and a tenth transistor coupled between the seventh node and the ground node that includes a gate coupled to the second bias output.
 9. The device of claim 1, further comprising: processing logic configured to control a sensor; and a wakeup timer coupled to the processing logic, wherein the wakeup timer includes the oscillator.
 10. The device of claim 1, wherein the set of stages is coupled in series in a ring.
 11. The device of claim 1, wherein each stage of the set of stages includes a load capacitance between the output node and the ground node.
 12. The device of claim 1, wherein a channel width of the sixth transistor is at least 1.3 times a channel width of the fourth transistor.
 13. The device of claim 12, wherein the channel width of the sixth transistor is about 3 times the channel width of the fourth transistor.
 14. A device comprising: a ring oscillator circuit that includes a set of stages that each include: an output node; a first transistor and a second transistor coupled in series between a voltage source node and the output node such that a first node is defined therebetween; a third transistor coupled between the first node and a ground node that includes a gate coupled to the output node; a fourth transistor and a fifth transistor coupled in series between the output node and a ground node such that a second node is defined therebetween; and a sixth transistor coupled between the second node and the voltage source node that includes a gate coupled to the output node.
 15. The device of claim 14, wherein each stage of the set of stages further includes: a first bias transistor coupled between the first transistor and the voltage source node; and a second bias transistor coupled between the fifth transistor and the ground node.
 16. The device of claim 15 further comprising: a bias circuit that includes a first bias output coupled to a gate of each first bias transistor of each stage of the set of stages and a second bias output coupled to a gate of each second bias transistor of each stage of the set of stages.
 17. The device of claim 16, wherein the bias circuit further includes: a resistor coupled between the voltage source node and a third node; a seventh transistor coupled between the third node and the second bias output that includes a gate coupled to the first bias output; and an eighth transistor coupled between the second bias output and the ground node that includes a gate coupled to the second bias output.
 18. The device of claim 16, wherein the bias circuit further includes: a ninth transistor coupled between the voltage source node and the first bias output that includes a gate coupled the first bias output; and a tenth transistor coupled between the first bias output and the ground node that includes a gate coupled the second bias output.
 19. The device of claim 16, wherein the bias circuit further includes a start-up circuit that includes: a capacitor coupled between the voltage source node and a fourth node; a ninth transistor coupled between the first bias output and the ground node that includes a gate coupled to the fourth node; and a tenth transistor coupled between the fourth node and the ground node that includes a gate coupled to the second bias output.
 20. The device of claim 15 further comprising a buffer coupled to the ring oscillator circuit that includes: a first buffer bias input coupled to a gate of each first bias transistor of each stage of the set of stages; a second buffer bias input coupled to a gate of each second bias transistor of each stage of the set of stages; a buffer input node coupled to the output node of a final stage of the set of stages of the ring oscillator circuit; and a buffer output node. 